DIGITAL BASICS (REVISION OF ENGINEERING COURSE WORK)

• Binary System, Logic Levels, Different Logic States, Noise Margins
• Combinational circuit & Sequential circuit, Frequency Divider/Multiplier circuit, Sequence Detector
• FSM (Mealy and Moore Models)

ADVANCE DIGITAL (IMPLEMENTATION OF DIGITAL CIRCUIT IN VLSI DESIGN)

• Designing of Different Logic gates/Combinational Circuit/Sequential elements using MUX
• PAL, PLA concepts, Tristate Buffers / Tristate Inverter, Clock Gating Concepts
• Standard Cell Library Concepts
• Logic Optimization

SEMICONDUCTOR OVERVIEW

• Property & Parameter : (Doping/Impurities, ,Amount of Impurities, Different type of Region (N+/N++, P+/P++),Energy Bands, Fermi Level, Drift Current, Mobility)
• Semiconductor Devices : (Depletion region, Built In potential, Immobile Ions, Diffusion Current, Recombination)

CMOS FUNDAMENTALS

• Basic : (Concepts of Vt in a MOS & Subthreshold Regions, MOS Electrical Parameters: Input output characteristics, How Source/Drain Terminals are defined, ,Cross Section of NMOS,PMOS,CMOS,Finfet Vs Planner CMOS)
• Advanced CMOS : (“Different factors on which Vt has dependency, Body Biasing, Channel Length Modulation”, FInFet Concepts, W/L Ration Concepts (Parallel and Series Connection), Parameter Variation (Fast and Slow Transistor) FF/SS CMOS, HVT / LVT / RVT Cells, Device Scaling)

CMOS CIRCUIT DESIGN

• CMOS Pass Transistor : (Switching Theory, NMOS and PMOS pass Transistor, Transmission Gate concepts, Pass transistor based problems)
• CMOS Circuit Design : (Designing of all Logic Gates, Combinational & Sequential Circuit)

CMOS FABRICATION

• Cross Section of CMOS,Single Tub/ Twin Tub, Single Well
• Device Cap and Metal Cap / CMOS Fabrication Process (Step by Step)
• Shallow Trench Isolation (STI layer), Latch Up Concepts

ADVANCE CMOS DESIGN

• CMOS Design : (Temperature Variation, Supply Voltage Variation, Process Variation, PVT Corners, Tap Cells, 3 Terminal & 4 Terminal Devices)
• Power Dissipations (Static , Dynamic Power, Transition Current, Short Circuit Power Dissipations, CMOS Leakages: Leakage related short circuit current, static current)

SCHEMATIC & SIMULATION CONCEPTS (INCLUDE PRACTICAL LABS)

• Schematic of Different Logic Gates : (BSIM Models, SPICE Netlist, Model Files)
• Fan-In, Fan-out, Driving Strength
• Introduction to Virtuoso/Tanner & different settings
• Technology File and different Inputs files

LAYOUT DESIGN (THEORITICAL CONCEPTS)

• Different layers Understanding, Metal Stack Concepts, Different DRC Rules & their understanding
• Layout drawing using Paper and Pen
• Fingering concepts
• TapCells , Nwell Cells Layout Concepts, Well Proximity Effect (WPE)
• Latchup and it’s preventions, Introduction of Guard Ring
• Placement of Standard cell in Design(Concepts of SiteRows/Grids/Tracks/Flipping of Standard Cells)
• Antenna Effects (Concepts, Damage, Remedies),Jumpers, Antenna Diode, Electromigration concepts and it’s preventions, AC/DC EM, IR Analysis, Power planning methods to reduce IR, Shielding Concepts

LAYOUT DESIGN (PRACTICAL TOOL BASED)

• Introduction to Virtuoso Layout window & different settings, Layout Pallets, GUI Interface
• Concepts of DRC, LVS, ERC and Basic Checks (Soft Check)
• Metal Stack based Design (Like Use both M1, M2 for design)

UNIX

• Overview of Unix platform & Different commands
• Shell Scripting: bash cshell,awk,sed
• VI editor concepts

TCL & PERL SCRIPTING

• TCL & Perl Introduction and it’s industrial use, Concepts of Wrapper,
• Procedure in TCL & regular expression
• File Handling, Read/Write Operation, Flow Control (Foreach, while, switches, for etc)
• Perl: List, Hash concepts

QOR AND REPORTING CONCEPTS

• Reporting concepts & different analysis concepts
• Log file and different type of Messages in that ( ERROR Messages, INFO Messages, WARNING Messages)
• Regression Concepts,Version to Version Check , Accuracy Check, Golden Vs Test Result
• Automation For Validation
• How to create charts, read charts, Histrogram, Pi charts concepts

LOGIC SYNTHESIS (BASIC)

• Introduction to Synthesis, Basic Terminology
• Netlist Overview with libraries introduction (Target Library, Link Library)
• Concept of Synthesizable RTL, Mapping to Gate level Netlist
• Different way of Modelling combinational or sequential elements

LOGIC SYNTHESIS (ADVANCE)

• Timing constraints basic (Max Trans, Max Cap, Max Fanout, Min cap)
• Commonly Faced Issues during Synthesis
• CDC and LINT Concepts
• DFT insertion basics inside synthesis tool

INTRODUCTION TO STATIC TIMING ANALYSIS & TIMING ARC

• Importance of Timing Analysis, VLSI Flow Introduction & different stages where Timing analysis happen
• Different component of Timing analysis (Timing Budgeting, Timing Constraint, Timing Check,Timing Violations, Fixing of Timing Violations
• Introduction about different input and output files for STA
• Importance of Timing Arc & Timing Arc Representation in .LIB Files

DELAY INTRODUCTION (CELL DELAY AND NET DELAY)

• Introduction of Delay Concepts
• Combinational Path Delays, Sequential Path Delays
• Net Delay basic (Metal Wire Concepts, Metal Stack concepts)
• Gate Delay Concepts (Charging & Discharging concepts, Load related Concepts, Delay dependency on current of Inverter, Internal Capacitance, Input Capacitance and Output Capacitance concepts

DELAY MODELS & UNDERSTANDING DELAYS LIBRARIES

• Gate Delay Models (How delay depends on Input Transition & Output Load, NLDM Library & CCS Library)
• Net Delay Models (Transmission Line Models, Elmore Model,Wire Load Model

STA TOOL DELAY CALCULATION METHODOLOGY

• Delay Calculation by STA tools (Path based Analysis and Graph Based Analysis)
• Pre-Layout Delay (using wire-load model) & Post layout Delay (using SPEF File) calculation
• Delay Calculation using Delay tables, Complexity across different corners.
• Dependency of Delay on different parameters (PVT Corners, Manufacturing defects, RC Corners)

TIMING PATHS, TIMING EXCEPTIONS & TIMING CONSTRAINTS

• Various Timing Paths (Data Path, Clock Path, Asynchronous Path, Clock Group Introduction
• Representation of Timing path within Timing report
• Timing Exceptions (False path, Multicycle path)
• Clock Constraints, Input and Output Delay constraints

SETUP AND HOLD TIME

• Different Timing Terminology (launch/capture path, Slew, Clock latency, Clock skew)
• Setup and Hold Time
• Setup and Hold Check and corresponding Equations
• Basic Timing Report

ADVANCED TIMING CONCEPTS

• Global Setup-hold time
• Onchip Variations (OCV),Advanced onchip Variation (AOCV),Setup and Hold Check in case of OCV, AOCV
• CRP & CRPR
• Multi-Mode Multi-Corner timing analysis

TIMING OPTIMIZATION & TIMING CLOSURE METHODS

• Pre-placement (After synthesis) optimization
• Pre-CTS (during or after placement or floorplaning) optimization
• Fixing of Setup and Hold Violation at Logic Synthesis (front-end vlsi)

POST LAYOUT STA (BACKEND) & FIXING SETUP AND HOLD VIOLATIONS METHODS

• Post CTS or Pre-Route (After CTS)Optimization
• Signoff Timing or Post-Route (After Routing) Timing Closure

SRAM

• SRAM Basic Concepts & SRAM Vs DRAM
• SRAM array architecture
• SRAM – Basic Read and write operation

FUNDAMENTAL OF DFT

• DFT ? Why, What, Who, When?
• Implementation of Digital Concepts in DFT & Different Terminology
• Test Concepts & Automatic Testing
• Timing Checks and Constraints, Timing concepts for DFT

DFT BASICS

• Introduction to BIST (Built-In Self Test)
• Introduction to BIT (Built-In Test)
• Scan Chain Concepts, Boundry scan chain
• Introduction of ATPG (Automatic Test Pattern Generation)

BASIC CONCEPTS

• Power Domain Concepts, Different Device powers (Leakage power, Static Power, Transition power)
• “Power Related Cells (Retention cell, Level shifter, Isolation Cell and other special cells)
• Low power concepts – Why we need it, UPF / CPF concepts – Why we need it

FLOW AND DESIGN BASICS

• Modular Approach / Hierarchical Approach, Top to bottom, Bottom to Top Approach
• Overview of RTL to Gatelevel  Netlist, Overview of Physical Design
• Modes (Functional, Test and others),MCMM, Case Analysis,
• Constraints (Physical Constraint, Design Constrainst, Power Constraints, Timing Constraints)
• Netlist,Pins/Ports/IO Pads /PG Pins, ,Design Corners (PVT and RC Corners)
• Timing Analysis Vs Timing Optimization,,Power Analysis Vs Power Optimization

UNDERSTANDING OF DIFFERENT INPUT/OUTPUT FILES

• LEF/DEF, Model Files
• Timing Library (.lib), SDC, Wireload,
• LVS Deck, DRC Deck, ERC Deck, Interconnect file, TLU+File/Cap tables, Parasitic Files (SPEF)

PHYSICAL DESIGN FLOW

• Floorplan
• Placement
• CTS
• Routing
• STA and Parasitic Extraction

VERILOG CONCEPTS

• Verilog Design Flow and Design Methodology
• Definition of Verilog Codes (Different Syntax)
• Different Type of Modelling (Gate level Modelling, Data Flow Modelling, Behavioural Modelling)
• Test Bench Writing concepts
• System Task Function